// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN:   -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma \
// RUN:   -target-feature +zve64x -target-feature +zve64d \
// RUN:   -target-feature +experimental-zvzip -disable-O0-optnone \
// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN:   FileCheck --check-prefix=CHECK-RV64 %s

#include <riscv_vector.h>

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vzip_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf4_t vs2,
                                     vfloat16mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_f16mf2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vzip_vv_f16m1_tu(vfloat16m1_t vd, vfloat16mf2_t vs2,
                                   vfloat16mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_f16m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vzip_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m1_t vs2,
                                   vfloat16m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_f16m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vzip_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m2_t vs2,
                                   vfloat16m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_f16m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vzip_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m4_t vs2,
                                   vfloat16m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_f16m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vzip_vv_f32m1_tu(vfloat32m1_t vd, vfloat32mf2_t vs2,
                                   vfloat32mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_f32m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vzip_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m1_t vs2,
                                   vfloat32m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_f32m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vzip_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m2_t vs2,
                                   vfloat32m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_f32m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vzip_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m4_t vs2,
                                   vfloat32m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_f32m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vzip_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m1_t vs2,
                                   vfloat64m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_f64m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vzip_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m2_t vs2,
                                   vfloat64m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_f64m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vzip_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m4_t vs2,
                                   vfloat64m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_f64m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_tu
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vzip_vv_i8mf4_tu(vint8mf4_t vd, vint8mf8_t vs2, vint8mf8_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i8mf4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_tu
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vzip_vv_i8mf2_tu(vint8mf2_t vd, vint8mf4_t vs2, vint8mf4_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i8mf2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_tu
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vzip_vv_i8m1_tu(vint8m1_t vd, vint8mf2_t vs2, vint8mf2_t vs1,
                               size_t vl) {
  return __riscv_vzip_vv_i8m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_tu
// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vzip_vv_i8m2_tu(vint8m2_t vd, vint8m1_t vs2, vint8m1_t vs1,
                               size_t vl) {
  return __riscv_vzip_vv_i8m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_tu
// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vzip_vv_i8m4_tu(vint8m4_t vd, vint8m2_t vs2, vint8m2_t vs1,
                               size_t vl) {
  return __riscv_vzip_vv_i8m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_tu
// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vzip_vv_i8m8_tu(vint8m8_t vd, vint8m4_t vs2, vint8m4_t vs1,
                               size_t vl) {
  return __riscv_vzip_vv_i8m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vzip_vv_i16mf2_tu(vint16mf2_t vd, vint16mf4_t vs2,
                                   vint16mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16mf2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vzip_vv_i16m1_tu(vint16m1_t vd, vint16mf2_t vs2,
                                 vint16mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vzip_vv_i16m2_tu(vint16m2_t vd, vint16m1_t vs2, vint16m1_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i16m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vzip_vv_i16m4_tu(vint16m4_t vd, vint16m2_t vs2, vint16m2_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i16m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vzip_vv_i16m8_tu(vint16m8_t vd, vint16m4_t vs2, vint16m4_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i16m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vzip_vv_i32m1_tu(vint32m1_t vd, vint32mf2_t vs2,
                                 vint32mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vzip_vv_i32m2_tu(vint32m2_t vd, vint32m1_t vs2, vint32m1_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i32m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vzip_vv_i32m4_tu(vint32m4_t vd, vint32m2_t vs2, vint32m2_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i32m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vzip_vv_i32m8_tu(vint32m8_t vd, vint32m4_t vs2, vint32m4_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i32m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vzip_vv_i64m2_tu(vint64m2_t vd, vint64m1_t vs2, vint64m1_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i64m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vzip_vv_i64m4_tu(vint64m4_t vd, vint64m2_t vs2, vint64m2_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i64m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vzip_vv_i64m8_tu(vint64m8_t vd, vint64m4_t vs2, vint64m4_t vs1,
                                 size_t vl) {
  return __riscv_vzip_vv_i64m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_tu
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vzip_vv_u8mf4_tu(vuint8mf4_t vd, vuint8mf8_t vs2,
                                  vuint8mf8_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8mf4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_tu
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vzip_vv_u8mf2_tu(vuint8mf2_t vd, vuint8mf4_t vs2,
                                  vuint8mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8mf2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_tu
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vzip_vv_u8m1_tu(vuint8m1_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1,
                                size_t vl) {
  return __riscv_vzip_vv_u8m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_tu
// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vzip_vv_u8m2_tu(vuint8m2_t vd, vuint8m1_t vs2, vuint8m1_t vs1,
                                size_t vl) {
  return __riscv_vzip_vv_u8m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_tu
// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vzip_vv_u8m4_tu(vuint8m4_t vd, vuint8m2_t vs2, vuint8m2_t vs1,
                                size_t vl) {
  return __riscv_vzip_vv_u8m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_tu
// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vzip_vv_u8m8_tu(vuint8m8_t vd, vuint8m4_t vs2, vuint8m4_t vs1,
                                size_t vl) {
  return __riscv_vzip_vv_u8m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vzip_vv_u16mf2_tu(vuint16mf2_t vd, vuint16mf4_t vs2,
                                    vuint16mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16mf2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vzip_vv_u16m1_tu(vuint16m1_t vd, vuint16mf2_t vs2,
                                  vuint16mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vzip_vv_u16m2_tu(vuint16m2_t vd, vuint16m1_t vs2,
                                  vuint16m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vzip_vv_u16m4_tu(vuint16m4_t vd, vuint16m2_t vs2,
                                  vuint16m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vzip_vv_u16m8_tu(vuint16m8_t vd, vuint16m4_t vs2,
                                  vuint16m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vzip_vv_u32m1_tu(vuint32m1_t vd, vuint32mf2_t vs2,
                                  vuint32mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m1_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vzip_vv_u32m2_tu(vuint32m2_t vd, vuint32m1_t vs2,
                                  vuint32m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vzip_vv_u32m4_tu(vuint32m4_t vd, vuint32m2_t vs2,
                                  vuint32m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vzip_vv_u32m8_tu(vuint32m8_t vd, vuint32m4_t vs2,
                                  vuint32m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vzip_vv_u64m2_tu(vuint64m2_t vd, vuint64m1_t vs2,
                                  vuint64m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u64m2_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vzip_vv_u64m4_tu(vuint64m4_t vd, vuint64m2_t vs2,
                                  vuint64m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u64m4_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], i64 [[VL]])
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vzip_vv_u64m8_tu(vuint64m8_t vd, vuint64m4_t vs2,
                                  vuint64m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u64m8_tu(vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vzip_vv_f16mf2_tum(vbool64_t vm, vfloat16mf2_t vd,
                                      vfloat16mf4_t vs2, vfloat16mf4_t vs1,
                                      size_t vl) {
  return __riscv_vzip_vv_f16mf2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vzip_vv_f16m1_tum(vbool32_t vm, vfloat16m1_t vd,
                                    vfloat16mf2_t vs2, vfloat16mf2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f16m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vzip_vv_f16m2_tum(vbool16_t vm, vfloat16m2_t vd,
                                    vfloat16m1_t vs2, vfloat16m1_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f16m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vzip_vv_f16m4_tum(vbool8_t vm, vfloat16m4_t vd,
                                    vfloat16m2_t vs2, vfloat16m2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f16m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vzip_vv_f16m8_tum(vbool4_t vm, vfloat16m8_t vd,
                                    vfloat16m4_t vs2, vfloat16m4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f16m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vzip_vv_f32m1_tum(vbool64_t vm, vfloat32m1_t vd,
                                    vfloat32mf2_t vs2, vfloat32mf2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f32m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vzip_vv_f32m2_tum(vbool32_t vm, vfloat32m2_t vd,
                                    vfloat32m1_t vs2, vfloat32m1_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f32m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vzip_vv_f32m4_tum(vbool16_t vm, vfloat32m4_t vd,
                                    vfloat32m2_t vs2, vfloat32m2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f32m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vzip_vv_f32m8_tum(vbool8_t vm, vfloat32m8_t vd,
                                    vfloat32m4_t vs2, vfloat32m4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f32m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vzip_vv_f64m2_tum(vbool64_t vm, vfloat64m2_t vd,
                                    vfloat64m1_t vs2, vfloat64m1_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f64m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vzip_vv_f64m4_tum(vbool32_t vm, vfloat64m4_t vd,
                                    vfloat64m2_t vs2, vfloat64m2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f64m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vzip_vv_f64m8_tum(vbool16_t vm, vfloat64m8_t vd,
                                    vfloat64m4_t vs2, vfloat64m4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_f64m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vzip_vv_i8mf4_tum(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
                                  vint8mf8_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8mf4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vzip_vv_i8mf2_tum(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
                                  vint8mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8mf2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vzip_vv_i8m1_tum(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
                                vint8mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vzip_vv_i8m2_tum(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
                                vint8m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vzip_vv_i8m4_tum(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
                                vint8m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vzip_vv_i8m8_tum(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
                                vint8m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vzip_vv_i16mf2_tum(vbool64_t vm, vint16mf2_t vd,
                                    vint16mf4_t vs2, vint16mf4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_i16mf2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vzip_vv_i16m1_tum(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
                                  vint16mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vzip_vv_i16m2_tum(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
                                  vint16m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vzip_vv_i16m4_tum(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
                                  vint16m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vzip_vv_i16m8_tum(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
                                  vint16m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vzip_vv_i32m1_tum(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
                                  vint32mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vzip_vv_i32m2_tum(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
                                  vint32m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vzip_vv_i32m4_tum(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
                                  vint32m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vzip_vv_i32m8_tum(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
                                  vint32m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vzip_vv_i64m2_tum(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
                                  vint64m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vzip_vv_i64m4_tum(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
                                  vint64m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vzip_vv_i64m8_tum(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
                                  vint64m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vzip_vv_u8mf4_tum(vbool64_t vm, vuint8mf4_t vd,
                                   vuint8mf8_t vs2, vuint8mf8_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u8mf4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vzip_vv_u8mf2_tum(vbool32_t vm, vuint8mf2_t vd,
                                   vuint8mf4_t vs2, vuint8mf4_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u8mf2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vzip_vv_u8m1_tum(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
                                 vuint8mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vzip_vv_u8m2_tum(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
                                 vuint8m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vzip_vv_u8m4_tum(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
                                 vuint8m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vzip_vv_u8m8_tum(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
                                 vuint8m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vzip_vv_u16mf2_tum(vbool64_t vm, vuint16mf2_t vd,
                                     vuint16mf4_t vs2, vuint16mf4_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_u16mf2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vzip_vv_u16m1_tum(vbool32_t vm, vuint16m1_t vd,
                                   vuint16mf2_t vs2, vuint16mf2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u16m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vzip_vv_u16m2_tum(vbool16_t vm, vuint16m2_t vd,
                                   vuint16m1_t vs2, vuint16m1_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u16m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vzip_vv_u16m4_tum(vbool8_t vm, vuint16m4_t vd, vuint16m2_t vs2,
                                   vuint16m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vzip_vv_u16m8_tum(vbool4_t vm, vuint16m8_t vd, vuint16m4_t vs2,
                                   vuint16m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vzip_vv_u32m1_tum(vbool64_t vm, vuint32m1_t vd,
                                   vuint32mf2_t vs2, vuint32mf2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u32m1_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vzip_vv_u32m2_tum(vbool32_t vm, vuint32m2_t vd,
                                   vuint32m1_t vs2, vuint32m1_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u32m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vzip_vv_u32m4_tum(vbool16_t vm, vuint32m4_t vd,
                                   vuint32m2_t vs2, vuint32m2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u32m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vzip_vv_u32m8_tum(vbool8_t vm, vuint32m8_t vd, vuint32m4_t vs2,
                                   vuint32m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vzip_vv_u64m2_tum(vbool64_t vm, vuint64m2_t vd,
                                   vuint64m1_t vs2, vuint64m1_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u64m2_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vzip_vv_u64m4_tum(vbool32_t vm, vuint64m4_t vd,
                                   vuint64m2_t vs2, vuint64m2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u64m4_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vzip_vv_u64m8_tum(vbool16_t vm, vuint64m8_t vd,
                                   vuint64m4_t vs2, vuint64m4_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_u64m8_tum(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vzip_vv_f16mf2_tumu(vbool64_t vm, vfloat16mf2_t vd,
                                       vfloat16mf4_t vs2, vfloat16mf4_t vs1,
                                       size_t vl) {
  return __riscv_vzip_vv_f16mf2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vzip_vv_f16m1_tumu(vbool32_t vm, vfloat16m1_t vd,
                                     vfloat16mf2_t vs2, vfloat16mf2_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f16m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vzip_vv_f16m2_tumu(vbool16_t vm, vfloat16m2_t vd,
                                     vfloat16m1_t vs2, vfloat16m1_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f16m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vzip_vv_f16m4_tumu(vbool8_t vm, vfloat16m4_t vd,
                                     vfloat16m2_t vs2, vfloat16m2_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f16m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vzip_vv_f16m8_tumu(vbool4_t vm, vfloat16m8_t vd,
                                     vfloat16m4_t vs2, vfloat16m4_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f16m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vzip_vv_f32m1_tumu(vbool64_t vm, vfloat32m1_t vd,
                                     vfloat32mf2_t vs2, vfloat32mf2_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f32m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vzip_vv_f32m2_tumu(vbool32_t vm, vfloat32m2_t vd,
                                     vfloat32m1_t vs2, vfloat32m1_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f32m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vzip_vv_f32m4_tumu(vbool16_t vm, vfloat32m4_t vd,
                                     vfloat32m2_t vs2, vfloat32m2_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f32m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vzip_vv_f32m8_tumu(vbool8_t vm, vfloat32m8_t vd,
                                     vfloat32m4_t vs2, vfloat32m4_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f32m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vzip_vv_f64m2_tumu(vbool64_t vm, vfloat64m2_t vd,
                                     vfloat64m1_t vs2, vfloat64m1_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f64m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vzip_vv_f64m4_tumu(vbool32_t vm, vfloat64m4_t vd,
                                     vfloat64m2_t vs2, vfloat64m2_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f64m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vzip_vv_f64m8_tumu(vbool16_t vm, vfloat64m8_t vd,
                                     vfloat64m4_t vs2, vfloat64m4_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f64m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vzip_vv_i8mf4_tumu(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
                                   vint8mf8_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8mf4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vzip_vv_i8mf2_tumu(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
                                   vint8mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8mf2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vzip_vv_i8m1_tumu(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
                                 vint8mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vzip_vv_i8m2_tumu(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
                                 vint8m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vzip_vv_i8m4_tumu(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
                                 vint8m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vzip_vv_i8m8_tumu(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
                                 vint8m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vzip_vv_i16mf2_tumu(vbool64_t vm, vint16mf2_t vd,
                                     vint16mf4_t vs2, vint16mf4_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_i16mf2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vzip_vv_i16m1_tumu(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
                                   vint16mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vzip_vv_i16m2_tumu(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
                                   vint16m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vzip_vv_i16m4_tumu(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
                                   vint16m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vzip_vv_i16m8_tumu(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
                                   vint16m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vzip_vv_i32m1_tumu(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
                                   vint32mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vzip_vv_i32m2_tumu(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
                                   vint32m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vzip_vv_i32m4_tumu(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
                                   vint32m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vzip_vv_i32m8_tumu(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
                                   vint32m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vzip_vv_i64m2_tumu(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
                                   vint64m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vzip_vv_i64m4_tumu(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
                                   vint64m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vzip_vv_i64m8_tumu(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
                                   vint64m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vzip_vv_u8mf4_tumu(vbool64_t vm, vuint8mf4_t vd,
                                    vuint8mf8_t vs2, vuint8mf8_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u8mf4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vzip_vv_u8mf2_tumu(vbool32_t vm, vuint8mf2_t vd,
                                    vuint8mf4_t vs2, vuint8mf4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u8mf2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vzip_vv_u8m1_tumu(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
                                  vuint8mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vzip_vv_u8m2_tumu(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
                                  vuint8m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vzip_vv_u8m4_tumu(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
                                  vuint8m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vzip_vv_u8m8_tumu(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
                                  vuint8m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vzip_vv_u16mf2_tumu(vbool64_t vm, vuint16mf2_t vd,
                                      vuint16mf4_t vs2, vuint16mf4_t vs1,
                                      size_t vl) {
  return __riscv_vzip_vv_u16mf2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vzip_vv_u16m1_tumu(vbool32_t vm, vuint16m1_t vd,
                                    vuint16mf2_t vs2, vuint16mf2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u16m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vzip_vv_u16m2_tumu(vbool16_t vm, vuint16m2_t vd,
                                    vuint16m1_t vs2, vuint16m1_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u16m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vzip_vv_u16m4_tumu(vbool8_t vm, vuint16m4_t vd,
                                    vuint16m2_t vs2, vuint16m2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u16m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vzip_vv_u16m8_tumu(vbool4_t vm, vuint16m8_t vd,
                                    vuint16m4_t vs2, vuint16m4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u16m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vzip_vv_u32m1_tumu(vbool64_t vm, vuint32m1_t vd,
                                    vuint32mf2_t vs2, vuint32mf2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u32m1_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vzip_vv_u32m2_tumu(vbool32_t vm, vuint32m2_t vd,
                                    vuint32m1_t vs2, vuint32m1_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u32m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vzip_vv_u32m4_tumu(vbool16_t vm, vuint32m4_t vd,
                                    vuint32m2_t vs2, vuint32m2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u32m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vzip_vv_u32m8_tumu(vbool8_t vm, vuint32m8_t vd,
                                    vuint32m4_t vs2, vuint32m4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u32m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vzip_vv_u64m2_tumu(vbool64_t vm, vuint64m2_t vd,
                                    vuint64m1_t vs2, vuint64m1_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u64m2_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vzip_vv_u64m4_tumu(vbool32_t vm, vuint64m4_t vd,
                                    vuint64m2_t vs2, vuint64m2_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u64m4_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vzip_vv_u64m8_tumu(vbool16_t vm, vuint64m8_t vd,
                                    vuint64m4_t vs2, vuint64m4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u64m8_tumu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vzip_vv_f16mf2_mu(vbool64_t vm, vfloat16mf2_t vd,
                                     vfloat16mf4_t vs2, vfloat16mf4_t vs1,
                                     size_t vl) {
  return __riscv_vzip_vv_f16mf2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vzip_vv_f16m1_mu(vbool32_t vm, vfloat16m1_t vd,
                                   vfloat16mf2_t vs2, vfloat16mf2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f16m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vzip_vv_f16m2_mu(vbool16_t vm, vfloat16m2_t vd,
                                   vfloat16m1_t vs2, vfloat16m1_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f16m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vzip_vv_f16m4_mu(vbool8_t vm, vfloat16m4_t vd,
                                   vfloat16m2_t vs2, vfloat16m2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f16m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vzip_vv_f16m8_mu(vbool4_t vm, vfloat16m8_t vd,
                                   vfloat16m4_t vs2, vfloat16m4_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f16m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vzip_vv_f32m1_mu(vbool64_t vm, vfloat32m1_t vd,
                                   vfloat32mf2_t vs2, vfloat32mf2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f32m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vzip_vv_f32m2_mu(vbool32_t vm, vfloat32m2_t vd,
                                   vfloat32m1_t vs2, vfloat32m1_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f32m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vzip_vv_f32m4_mu(vbool16_t vm, vfloat32m4_t vd,
                                   vfloat32m2_t vs2, vfloat32m2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f32m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vzip_vv_f32m8_mu(vbool8_t vm, vfloat32m8_t vd,
                                   vfloat32m4_t vs2, vfloat32m4_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f32m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vzip_vv_f64m2_mu(vbool64_t vm, vfloat64m2_t vd,
                                   vfloat64m1_t vs2, vfloat64m1_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f64m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vzip_vv_f64m4_mu(vbool32_t vm, vfloat64m4_t vd,
                                   vfloat64m2_t vs2, vfloat64m2_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f64m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vzip_vv_f64m8_mu(vbool16_t vm, vfloat64m8_t vd,
                                   vfloat64m4_t vs2, vfloat64m4_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_f64m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vzip_vv_i8mf4_mu(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
                                 vint8mf8_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8mf4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vzip_vv_i8mf2_mu(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
                                 vint8mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8mf2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vzip_vv_i8m1_mu(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
                               vint8mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vzip_vv_i8m2_mu(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
                               vint8m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vzip_vv_i8m4_mu(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
                               vint8m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vzip_vv_i8m8_mu(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
                               vint8m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i8m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vzip_vv_i16mf2_mu(vbool64_t vm, vint16mf2_t vd,
                                   vint16mf4_t vs2, vint16mf4_t vs1,
                                   size_t vl) {
  return __riscv_vzip_vv_i16mf2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vzip_vv_i16m1_mu(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
                                 vint16mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vzip_vv_i16m2_mu(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
                                 vint16m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vzip_vv_i16m4_mu(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
                                 vint16m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vzip_vv_i16m8_mu(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
                                 vint16m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i16m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vzip_vv_i32m1_mu(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
                                 vint32mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vzip_vv_i32m2_mu(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
                                 vint32m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vzip_vv_i32m4_mu(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
                                 vint32m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vzip_vv_i32m8_mu(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
                                 vint32m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vzip_vv_i64m2_mu(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
                                 vint64m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vzip_vv_i64m4_mu(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
                                 vint64m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vzip_vv_i64m8_mu(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
                                 vint64m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_i64m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vzip_vv_u8mf4_mu(vbool64_t vm, vuint8mf4_t vd, vuint8mf8_t vs2,
                                  vuint8mf8_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8mf4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vzip_vv_u8mf2_mu(vbool32_t vm, vuint8mf2_t vd, vuint8mf4_t vs2,
                                  vuint8mf4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8mf2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vzip_vv_u8m1_mu(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
                                vuint8mf2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vzip_vv_u8m2_mu(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
                                vuint8m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vzip_vv_u8m4_mu(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
                                vuint8m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vzip_vv_u8m8_mu(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
                                vuint8m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u8m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vzip_vv_u16mf2_mu(vbool64_t vm, vuint16mf2_t vd,
                                    vuint16mf4_t vs2, vuint16mf4_t vs1,
                                    size_t vl) {
  return __riscv_vzip_vv_u16mf2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vzip_vv_u16m1_mu(vbool32_t vm, vuint16m1_t vd,
                                  vuint16mf2_t vs2, vuint16mf2_t vs1,
                                  size_t vl) {
  return __riscv_vzip_vv_u16m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vzip_vv_u16m2_mu(vbool16_t vm, vuint16m2_t vd, vuint16m1_t vs2,
                                  vuint16m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vzip_vv_u16m4_mu(vbool8_t vm, vuint16m4_t vd, vuint16m2_t vs2,
                                  vuint16m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vzip_vv_u16m8_mu(vbool4_t vm, vuint16m8_t vd, vuint16m4_t vs2,
                                  vuint16m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u16m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vzip_vv_u32m1_mu(vbool64_t vm, vuint32m1_t vd,
                                  vuint32mf2_t vs2, vuint32mf2_t vs1,
                                  size_t vl) {
  return __riscv_vzip_vv_u32m1_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vzip_vv_u32m2_mu(vbool32_t vm, vuint32m2_t vd, vuint32m1_t vs2,
                                  vuint32m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vzip_vv_u32m4_mu(vbool16_t vm, vuint32m4_t vd, vuint32m2_t vs2,
                                  vuint32m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vzip_vv_u32m8_mu(vbool8_t vm, vuint32m8_t vd, vuint32m4_t vs2,
                                  vuint32m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u32m8_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vzip_vv_u64m2_mu(vbool64_t vm, vuint64m2_t vd, vuint64m1_t vs2,
                                  vuint64m1_t vs1, size_t vl) {
  return __riscv_vzip_vv_u64m2_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vzip_vv_u64m4_mu(vbool32_t vm, vuint64m4_t vd, vuint64m2_t vs2,
                                  vuint64m2_t vs1, size_t vl) {
  return __riscv_vzip_vv_u64m4_mu(vm, vd, vs2, vs1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vzip_vv_u64m8_mu(vbool16_t vm, vuint64m8_t vd, vuint64m4_t vs2,
                                  vuint64m4_t vs1, size_t vl) {
  return __riscv_vzip_vv_u64m8_mu(vm, vd, vs2, vs1, vl);
}
