A scratchpad for random thoughts re spudstop.
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Reading MHz on an ACPI kernel gets us wild results, anywhere
between 2MHz and 266MHz. The reason for this is that the
ACPI code does thermal throttling unrelated to Speedstep
(ACPI C-States).

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ICH2-M and ICH3-M support is in the 2.5 - release of cpufreq.
This "2nd type of speedstep" can be supported without reverse-
engineering by using a documented interface in this chipset.

The previsiously mentioned 0xB2 port is an APM interface, for 
the time being these thoughts are kept just in case they are
needed again:

##################
Malik Martin <martin.malik@siemens.at> has reverse engineered
large amounts of the 2nd type of speedstep (ICH).
His findings follow.

Everyting is done using a BYTE-write to port 0xB2 (which is also mentioned
in the MS document), but the behavior is REALLY STRANGE, because this
instruction uses other registers (than DX, AL) and upon completion changes
registers !! Yes, it's hard to believe, because I haven't seen such a
behavior yet.

Set EAX to 0x47534982, where AL=0x82 is a special command byte.
The rest of EAX means "GSI" in ASCII, but why ???
Register EBX seems to be the function select register.
Then perform a BYTE write to port 0xB2 (OUT DX,AL).
Now if it worked, you can see, that also other registers have changed.
I assume, that if the CPU/chipset gets I/O write to 0xB2 with 0x82 it
compares
the rest of EAX with "GSI" and if true, it acts different.
So, following is a description of functions, that I found:

EBX=0 - ???
Return:
EAX=0
EDI=??? (00000004)

--------------------------

EBX=1 - Get state
Return:
EAX=0 => success?
EBX=Current state
EDI=??? (0202FE05)
ESI=??? (00000900)

Function 1 returns in EDI: bit0 power supply: 0=battery, 1=main
--------------------------

EBX=2 - Set state
ECX=desired state
Return: EDI=0 => success
EBX=new state

--------------------------

State: 0=Maximum perf., 1=Battery optimized

Example in ASM to change the power state to Battery optimized mode:

MOV EAX,47534982h
MOV EBX,2
MOV EDX,000000B2h
MOV ECX,1
OUT DX,AL
####################


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PIIX4 support still has to be reverse-engineered as Intel
continues to withhold the documentation for this "1st type
of speedstep".

